┌────────────────────────────────────────────────┐ │ IT8995E-128 (LQFP-128) │ │ │ LPC Bus ──┤ LPC Interface → Register Bank → Internal Bus │ │ │ │ │ ├── UART A (with 128-byte FIFO) ── COM1 │ │ ├── UART B (with 128-byte FIFO) ── COM2 │ │ ├── Parallel Port (EPP/ECP) ─────── LPT1 │ │ ├── PS/2 Controller ───────────── KBC/MSC│ │ ├── Fan Control (PWM + Tach) ────── FAN1-4│ │ ├── 12-bit ADC (8 channels) ─────── Volt/Temp│ │ ├── SMBus 2.0 Master/Slave ─────── SMBus│ │ ├── CIR Decoder/Encoder ────────── Infrared│ │ └── GPIO Matrix (64 pins) ────────── GPIO0-63│ │ │ │ ┌───────┐ ┌────────┐ ┌──────────┐ │ │ │ Power │ │ Clock │ │ Watchdog│ │ │ │ Mgmt. │ │ Gen. │ │ Timer │ │ │ └───────┘ └────────┘ └──────────┘ │ └────────────────────────────────────────────────┘ The IT8995E-128 datasheet stresses the importance of staying within these limits to avoid permanent damage:
| Symbol | Parameter | Min | Max | Unit | |--------|-----------|-----|-----|------| | VCC | Supply voltage | -0.3 | +4.0 | V | | VIN | Input voltage (5V tolerant) | -0.3 | +5.5 | V | | IOH | Output high current per pin | - | 8 | mA | | IOL | Output low current per pin | - | 16 | mA | | TSTG | Storage temperature | -55 | +125 | °C | | TJ | Junction temperature | - | +125 | °C | it8995e 128 datasheet
| Register Offset | Name | Description | |----------------|------|-------------| | 0x07 | Logical Device Number | Select active device (UART, LPT, GPIO, etc.) | | 0x21 | GPIO Direction | 0 = input, 1 = output | | 0x22 | GPIO Polarity Inversion | 1 = invert input | | 0x24 | GPIO Pull-up Enable | Internal 100kΩ pull-up | | 0x60–0x67 | Base Address Registers | I/O base for UART/LPT | | 0x70 | Interrupt Select | IRQ mapping (3,4,5,7,9,10,11,12) | | 0x71 | Fan Tachometer Divisor | Sets measurement range | Introduction The IT8995E-128 is a highly integrated Super
This article consolidates the critical information from the , including electrical characteristics, pin configuration, functional blocks, and application circuits. Whether you are reverse-engineering a motherboard, developing BIOS firmware, or sourcing components for a repair, this guide serves as a practical datasheet companion. Key Features of the IT8995E-128 (Based on Official Datasheet) According to the IT8995E-128 datasheet , the chip operates within the following parameters: particularly for industrial PCs
| Pin | Signal | Description | |------|--------|-------------| | 1 | LCLK | 33 MHz clock from PCH | | 2 | LFRAME# | Frame signal for cycle start/end | | 3 | LRST# | LPC reset (active low) | | 4 | LAD0 | Multiplexed address/data line 0 | | 5 | LAD1 | Multiplexed address/data line 1 | | 6 | LAD2 | Multiplexed address/data line 2 | | 7 | LAD3 | Multiplexed address/data line 3 | | 8 | LDRQ# | DMA request line | | 9–12 | GND | Digital ground | Most pins on the IT8995E-128 are multi-function. The datasheet defines a register map to select between GPIO, UART, fan control, or ADC input.
Introduction The IT8995E-128 is a highly integrated Super I/O (Input/Output) controller manufactured by ITE (Integrated Technology Express, Inc.). This chip is a cornerstone of modern motherboard design, particularly for industrial PCs, embedded systems, and high-end consumer laptops. Unlike basic I/O controllers, the IT8995E-128 bridges legacy interfaces (PS/2, LPC, UART) with advanced system management features.